The subject application is related to subject matter disclosed in Japanese Patent Application No. H12-20810 filed on Jan. 28, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to a voltage comparator circuit in a CMOS integrated circuit. More specifically, the invention relates to a voltage comparator circuit for comparing voltages close to a ground or power supply potential, the voltage comparator circuit being used for detecting the occurrence of abnormality, such as a case where a p-n junction between the source and substrate of a CMOS integrated circuit is biased in a forward direction, in the control of a substrate potential.
2. Description of the Background Art
FIG. 7 shows a MOS differential amplifier circuit which is conventionally often used for comparing voltages.
The sources of a pair of N-channel MOS transistors (which will be hereinafter referred to as NMOS transistors) M101 and M102 are commonly connected to be grounded via a current source I100. The gate of the NMOS transistor M101 is connected to an input terminal IN to which a signal VIN is inputted. The gate of the NMOS transistor M102 is connected to an input terminal INN to which a signal VINN having the opposite phase to that of the input terminal IN is inputted. One end of a resistor R101 is connected to the node a of the drain of the NMOS transistor M101, and the other end thereof is connected to a power supply VDD. One end of a resistor R102 is connected to the node b of the drain of the NMOS transistor M102, and the other end thereof is connected to a power supply VDD. The node a is connected to the input terminal of a buffer S1 to derive a signal from an output terminal OUT. In place of the signal VINN, a reference voltage Vref for comparing voltages may be applied to the input terminal INN.
The principle of operation of the differential amplifier circuit with this construction is well known as follows. The potential difference between the input terminals IN and INN causes a difference between the gate-to-source voltages VGSxe2x80x94M101 and VGSxe2x80x94M102 of the NMOS transistors M101 and M102, to cause a difference between the proportions of currents of the NMOS transistors M101 and M102, into which a current I100 supplied from the current source I100 is divided, i.e., a difference between a drain current IDxe2x80x94M101 of the NMOS transistor M101 and a drain current IDxe2x80x94M102 of the NMOS transistor M102. These relationships are expressed as follows:
IDxe2x80x94M101=k(VGSxe2x80x94M101xe2x88x92Vth)2xe2x80x83xe2x80x83(Expression 1)
IDxe2x80x94M102=k(VGSxe2x80x94M102xe2x88x92Vth)2xe2x80x83xe2x80x83(Expression 2)
IDxe2x80x94M101+IDxe2x80x94M102=I100xe2x80x83xe2x80x83(Expression 3)
wherein Vth is the threshold voltage of the MOS transistor. The coefficient k is defined by the following expression using a gate width W, a gate length L, a gate capacity COX and a mobility xcexcn of electrons in Si.
K=xc2xdxcexcnCOXW/Lxe2x80x83xe2x80x83(Expression 4)
The drain currents IDxe2x80x94M101 and IDxe2x80x94M102 derived from the difference between the gate-to-source voltages VGSxe2x80x94M101 and VGSxe2x80x94M102 on the basis of the above described expressions are as follows.
IDxe2x80x94M101=I100/2+k(VGSxe2x80x94M101xe2x88x92VGSxe2x80x94M102)/2{square root over ( )}{2I100/kxe2x88x92(VGSxe2x80x94M101xe2x88x92VGSxe2x80x94M102)2}xe2x80x83xe2x80x83(Expression 5)
IDxe2x80x94M102=I100/2xe2x88x92k(VGSxe2x80x94M101xe2x88x92VGSxe2x80x94M102)/2{square root over ( )}{2I100/kxe2x88x92(VGSxe2x80x94M101xe2x88x92VGSxe2x80x94M102)2}xe2x80x83xe2x80x83(Expression 6)
A voltage is derived from the output terminal OUT via the buffer S1 having a voltage Va of the node a which is generated by the current IDxe2x80x94M101 flowing through the resistor R101. The voltage Va of the node a is expressed as follows.
Va=VDDxe2x88x92IDxe2x80x94M101R101xe2x80x83xe2x80x83(Expression 7)
This conventional circuit has a comparable voltage range of from about 0 V to a power supply voltage. If the reference potential Vref for comparing voltages is set to be 0 V or the power supply voltage to be used for comparing voltages approximating to the ground or power supply potential, there is a problem. If the reference potential Vref is set to be 0 V and if the voltage of the input terminal IN is set to be about 0 V, the source potentials of the NMOS transistors M101 and M102 become to negative potentials since the sources of the NMOS transistors M101 and M102 are connected to the ground potential via the current source. However, it is generally difficult to generate such negative potentials, if the reference potential Vref=0 V is applied to the input terminal INN, the gate-to-source voltage VGSxe2x80x94M102 of the NMOS transistor M102 is below the threshold voltage, so that the NMOS transistor M102 is always turned off so as not to be operated. If the reference potential Vref is set to be the power supply potential and if the voltage of the input terminal IN is set to approximate to the power supply voltage, the source potentials of the NMOS transistors M101 and M102 increase. Therefore, there is a limit to the amplitude of the voltage Va of the node a which is the drain of the NMOS transistor M101, so that the buffer is difficult to receive signals.
Accordingly, if lower voltages than the ground potential are compared with each other, a differential amplifier circuit shown in FIG. 8 has been conventionally used. A level shifter circuit is added for converting voltages which are applied to the gates of NMOS transistors M111 and M112. One end of a resistor R121 is connected to an input terminal IN, and the other end thereof is connected to a constant current source I121 and the gate of the NMOS transistor M111. One end of a resistor R122 is connected to an input terminal INN, and the other end thereof is connected to a constant current source I122 and the gate of the NMOS transistor M112. By always passing currents I121 and I122 through the resistors R121 and R122, the voltages of the other ends of the resistors R121 and R122 are shifted by a predetermined voltage with respect to the input terminals IN and INN. Thus, even if lower voltages than the ground potential are compared with each other, the gate potentials of the NMOS transistors M111 and M112 can be in the range of from about 0 V to the power supply voltage, which is a voltage range capable of being compared by conventional circuits. However, in this method, there are problems in that current consumption increases since the currents I121 and I122 must be passed through the level shifter circuit and that the currents I121 and I122 are passed through the input terminals. In the case of a voltage comparator circuit for use in the detection of a substrate potential, it is desired to prevent such currents from passing through the input terminals into the substrate. Because the burden imposed on a substrate bias generating circuit is increased by the currents, which thus flow into the substrate, to increase current consumption.
There is also considered a method for changing the ground potential, to which the current source I100 of the differential amplifier circuit shown in FIG. 7 is connected, into a negative potential to increase the range of comparable input voltages. However, in this method, there is a problem in that it is required to additionally provide a power supply voltage.
A simple circuit shown in FIG. 9 is also known. The source of an NMOS transistor M130 is connected to the ground potential, the drain thereof is connected to one end of a resistor R130 and the input terminal of a buffer S1, and the gate thereof is connected to an input terminal IN. The other end of the resistor R130 is connected to a power supply potential VDD, and the output terminal of the buffer S1 is connected to an output terminal OUT. With this construction, if the voltage VIN of the input terminal IN is higher than the threshold voltage of the NMOS transistor M130, the NMOS transistor M130 is turned on to pass its drain current through the resistor R130 to decrease the voltage of the input terminal of the buffer S1, so that the signal level of the output terminal OUT changes from a low level to a high level.
Thus, in this case, the voltage serving as a reference for comparison is the threshold voltage of the NMOS transistor M130, so that there are problems in that the detectable voltage must be slightly higher than the ground potential and that the circuit is easily influenced by the variation in device and temperature.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a voltage comparator circuit capable of simply and precisely comparing a voltage with a ground or power supply potential.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, there is provided a voltage comparator circuit comprising: a pair of first and second MOS transistors of a conductive type, the gates of which are commonly connected, and each of the drains of which is connected to a first power supply potential via a current source for passing the same current, the first and second MOS transistors having the same gate width and gate length; a third MOS transistor of the opposite conductive type to that of the first and second MOS transistors, the drain of the third MOS transistor being connected to a second power supply potential, and the source of the third MOS transistor being connected to the source of the first MOS transistor; and a fourth MOS transistor of the opposite conductive type to that of the first and second MOS transistors, the drain of the fourth MOS transistor being connected to the second power supply potential, and the source of the fourth MOS transistor being connected to the source of the second MOS transistor, the fourth MOS transistor having the same gate width and gate length as those of the third MOS transistor, wherein the drain and gate of the first MOS transistor are connected to each other, and a comparative reference potential is applied to the gate of the third MOS transistor, and wherein an input signal is given to the gate of the fourth MOS transistor, and an output signal is derived from the drain of the second MOS transistor.
With this construction, it is possible to precisely compare voltages without the need of any level converting means and a plurality of power sources.
If the voltage comparator circuit further comprises a differential amplifier for comparing a voltage at the drain of the first MOS transistor with a voltage at the drain of the second MOS transistor, it is possible to cancel the difference between the characteristics of elements due to the variation in producing process and temperature change, in addition to the above described effect.
According to another aspect of the present invention, there is provided a substrate bias adjusting circuit comprising: circuit means for detecting that a P-well potential is higher than a ground potential, to produce a signal; and circuit means for short-circuiting the P-well potential to the ground potential on the basis of the signal to rapidly return the P-well potential to the ground potential.
According to a further aspect of the present invention, there is provided a substrate bias adjusting circuit comprising: circuit means for detecting that an N-well potential is lower than a power supply potential, to produce a signal; and circuit means for short-circuiting the N-well potential to the power supply potential on the basis of the signal to rapidly return the N-well potential to the power supply potential.